1. Field of the Invention
This invention relates to integrated circuit semiconductor chip packages and more particularly to semiconductor chip carrier, first level electronic packages having high frequency decoupling capacitors as a part of the package.
2. Background Information
As very large scale integrated (LSI) circuits tend to get more complex, there is a need to switch more output driver circuits at a faster rate in order to increase the performance thereof. Moreover, an increase in the use of parallel processing techniques have necessitated designing semiconductor chip carriers for optimum performance of the LSI circuits. Similarly, these techniques require a high number of driver circuits to switch simultaneously at fast transition speeds and high currents. The effective inductance of semiconductor chip and package power paths for these active switching circuits relates directly to the amount of power distribution noise. Power paths which feed the driver circuits are particularly noise sensitive to the inherent effective inductance for simultaneous switching activity. Various techniques have been utilized in the art to minimize the level of switching noise associated with the increase and the magnitude of the switching rate.
One known technique for reducing the level of noise is to incorporate discrete capacitors as a decoupling capacitor between associated voltage pins. Generally, the discrete capacitors, which are mounted on a top surface of a carrier and distance away from the semiconductor chip, is electrically coupled thereto by a plurality of power wiring lines or a large power buses. This technique of positioning the discrete capacitors on the top surface of a carrier reduces the wireability on the top surface. Moreover, the power wiring lines typically represent long inductances paths which, in response to the increase in current flowing therein, facilitate the development of voltage drops thereacross. The voltage drops are viewed as unwanted power distribution noise. One technique of minimizing the inductances paths is move the discrete capacitors as close to the semiconductor chip as possible. However, in view of either the layout of the wiring lines on the top surface associated with the semiconductor chip or the physical dimensions of the discrete capacitor, this technique does not result in a substantial reduction in the inductance paths and the noise associated therewith.
Consequentially, there is a need for a technique which reduces the noise associated with the increase in the rate which the current switches, minimizes the inductances paths and maximizes the wireability of the top surface of the carrier associated with the semiconductor chip.